The semiconductor industry makes wide use of copper conductive lines and interconnect structures in the construction of semiconductor devices. Copper has proven to be a very useful material for a number of reasons. For example, copper has a lower resistivity than aluminum. As a result, copper circuitry suffers less from resistance-capacitance (RC) delays. This makes copper systems faster.
However, copper has the disadvantage of high diffusivity through dielectric and silicon materials on which the copper is deposited. This is especially problematic when used with so-called low-K dielectric materials, which are coming into increasingly common usage. Diffusion of copper into insulating layers comprised of low-K dielectric materials can result in serious problems. Diffusion of copper into low-K materials typically “poisons” the materials so that semiconductor device failure is common. The industry has adapted to this problem by implementing barrier layers to prevent the diffusion of copper into the affected materials. Typically, the barrier materials consist of thin layers of material interposed between copper layers and low-K dielectric layers.
Although such barrier layers are effective at preventing the diffusion of copper materials, such barrier layers come with their own set of process difficulties. One such problem is that barrier layers can contribute to electromigration induced voiding in copper interconnect structures. Such voiding is a common source of circuit failure in copper based semiconductor structures. Such voiding is particularly problematic when it occurs in via structures. Research has shown that electromagnetic voiding is particularly common at the interface between the copper layer and the barrier layer.
This problem can be illustrated with reference to the schematic cross-section views illustrated in FIG. 1(a) and FIG. 1(b). In FIG. 1(a), a conventional semiconductor substrate 100 is depicted. A wafer surface 102 is depicted with a metal interconnect line 104 formed therein. Such wafers 102 are commonly formed of silicon or doped silicon. The metal interconnect line 104 is typically formed using copper or copper-containing materials (e.g., copper alloys or copper laminates and the like). An insulating layer 105 comprised of electrically insulating material (e.g., SiO2, low-K dielectrics, and other like materials) is formed over the wafer surface 102. In order to make electrical connections to overlying layers (not shown) openings 108 are formed in the insulating layer 105 to expose the underlying metal interconnect line 104. Such openings 108 are commonly formed using damascene or dual-damascene fabrication processes. A barrier layer 106 is commonly formed on the wafer surface 102 covering the insulating layer 105 and also covering the bottom and sidewalls of the opening 108. Subsequently, a plug 107 is formed in the opening 108 to form a via structure. The plug 107 is formed of a copper or copper-containing material constructed using ordinary fabrication techniques known to persons having ordinary skill in the art. The barrier layer 106 prevents diffusion of the copper from the plug 107 into the insulating layer 103.
An additional feature of such structures are the presence of minute voids 105 in the interconnect line 104. During the ordinary operation of integrated circuit structures containing such copper interconnects, copper atoms migrates within the interconnect lines 104. Additionally, it has been determined that one of the major pathways for such copper migration is the interface 110 between the interconnect line 104 and the barrier layer 106. Under certain common operating conditions this copper migration causes the voids 105 to move. In the depicted embodiment, the voids 105 move in a direction indicated by the arrow 111. Over time the migrating voids 105 tend to aggregate.
As depicted in FIG. 1(b) the aggregate voids 105′ can become quite sizable. In fact the aggregate voids 105′ can be come so large that they occlude the conduction pathways in the interconnect lines 104. Also, the aggregate voids 105′ can occlude the connections between certain vias and the interconnect lines. FIG. 1(b) depicts this problem. The aggregate void 105′ has migrated to the interface between the plug 107 and the interconnect line 104. Also, the aggregate void 105′ has grown so large that it destroys the current path between the plug 107 and the interconnect line 104. Current solutions to this problem require that a secondary via be constructed so that when one via fails a conduction path can still be achieved through the secondary via. Although such solutions work well enough for their intended purpose, improved solutions are desirable.